The present invention relates to a pair of MOS (metal-oxide-semiconductor) transistors, and a manufacturing method thereof. A MOS transistor, or MOSFET (for metal-oxide-semiconductor-field-effect-transistor) is an insulated-gate field-effect transistor in which the insulating layer between each gate terminal and the channel is oxide material.
Integrated circuits require using different types of transistors: short channel transistors for logic operations, small surface transistor for memories (SRAM) and large channel surface for analog transistors.
In an integrated circuit, transistors of the same type must have a low dispersion of their technical features. Requirement specification on this dispersion depends on the function of the transistors in the integrated circuit.
Typically, with analogic function such as current mirror, two transistors are supposed to have same electrical parameters. They are then called a pair of matched transistors.
A generally analyzed parameter to check the low dispersion between transistors of a pair is the threshold voltage difference between the two transistors of said pair, since variations between these threshold voltages cause efficiency fluctuations, increase electrical consumption, eventually decrease manufacturing efficiency and eventually threaten the circuit functionality.
For analog transistors, threshold voltage difference between matched transistors is typically desired to be less than 1 mV.
With bulk silicon technology, dispersion predominantly results from Random Dopant Fluctuation (RDF), which results from variation in the impurities (or dopants) concentration in the channel region of a MOSFET and can alter the properties of the transistor, especially the threshold voltage VT.
Due to its randomness, this dispersion source tends to decrease as the transistor surface increases, due to averaging of dopant concentration.
Thus, when a person skilled in the art wants to have matched transistors, i.e. with substantially similar features, he uses transistors with large surfaces, i.e. whose channel surfaces are large. In particular, large surface transistors are used in pair for structures defining current references, current mirrors, or current comparator.
With the fully depleted silicon on insulator (FD-SOI) technology, transistors are built upon a thin layer of silicon over a Buried Oxide (commonly called BOx), said thin layer of silicon being undoped, or fully-depleted. Consequently, the predominance of Random Dopant Fluctuation as a dispersion source is suppressed.
A new source of dispersion is however introduced with respect to bulk silicon: channel silicon thickness TSi of transistor channel may substantially vary among transistors. Since threshold voltage VT depends on channel silicon thickness TSi, variation of channel silicon thickness TSi causes variation of threshold voltage VT.
FIG. 1 illustrates a sectional view of an SOI substrate to show an example of channel silicon thickness difference ΔTSi between two transistors. A silicon layer 1 is built over a Buried Oxide layer 2. The channel silicon thickness TSi of said silicon layer 1 shows spatial variations due to the manufacturing process. The respective heights of surfaces 13 and 14 schematically represent the average channel silicon thickness under the corresponding top surfaces S13, S14 of the silicon layer covered by two transistor channels of a pair of transistors, respectively.
Accordingly, the height of the surface 13 represents the average channel silicon thickness under the surface S13 of a first transistor built on top of silicon layer 1, and arranged on the left-hand side of the pair in FIG. 1. The height of the surface 14 represents the average channel silicon thickness under the surface S14 of a second transistor built on top of silicon layer 1, and arranged on the right-hand side of the pair in FIG. 1.
For the sake of simplicity, depicted surfaces such as surfaces 13 and 14 will be assimilated to their respective transistors as a graphical way to represent the relation between channel surface and average channel silicon thickness for the transistors.
As seen on FIG. 1, average channel silicon thickness under the left-hand side transistor is less than average channel silicon thickness under the right-hand side transistor. This channel silicon thickness difference ΔTSi causes variation of threshold voltage VT between the two transistors.
FIG. 2 shows that the distance between the respective centers of transistors is important. As depicted on FIG. 2, left-hand side transistor 13 can be paired with a first transistor 14a in its vicinity, at a short distance Da. The resulting channel silicon thickness difference ΔTSi1 is relatively low. Should this left-hand side transistor 13 be paired with a second transistor 14b instead of the first transistor 14a, said second transistor being arranged at a greater distance Db from transistor 13, the resulting channel silicon thickness difference ΔTSi2 can be much greater.
For smaller transistors, i.e. with a small surface channel, threshold voltage VT variations induced by channel silicon thickness differences are not the predominant sources of dispersion. Indeed, random sources of dispersion such as Random Dopant Fluctuation (RDF) have a greater effect on the electrical parameters of the transistors.
This side effect is however especially detrimental for large surface transistors, i.e. with a large surface channel. Because they cover a large surface, the average channel silicon thicknesses of two transistors can significantly differ.
FIG. 3 illustrates a configuration similar to FIG. 1 with larger surface transistors. Due to greater spatial extension of the transistors, the channel silicon thickness difference ΔTSi between the two transistors 23, 24 is increased.
In FIG. 4, an even greater spatial extension, i.e. channel surface, of the transistors 33, 34 results in greater channel silicon thickness difference ΔTSi.
It shall be noted that this is the same with any technology wherein the substrate has a buried interface which delimits the active region thickness of the channel of transistors. The buried interface is a change of material which confines the charge carriers contributing to the conduction (e.g. electrons for N-MOS transistors or holes for P-MOS transistors) in the active region. Delimiting the active region depth of the channel means that the active region may not extend beyond said interface, due to differences in electrical characteristics between the material under said buried interface and the substrate.
For example, the buried interface may be an interface between the silicon of the channel and an insulating substrate or an interface between the silicon of the channel and a buried layer distinct from the substrate. Said buried interface also defines the channel silicon thickness of the transistor. Such thicknesses consideration will be referred to as channel silicon thickness in the following description. Preferably, the active region has a thickness under 15 nm.
Preferably, the active region is fully depleted in the depletion region, i.e. with a doping concentration substantially equals to or inferior to 1017 cm−3 for the depletion region, for example 3 nm under the gate oxide, and under 1018 cm−3 for the whole active region.
The buried interface can thus be defined by an insulating layer such as in the Silicon-on-Insulator technology, and the active region is then the thin film of silicon above the insulating layer. An exemplary embodiment uses the FD-SOI technology, and the buried interface is then the interface between the Box and the thin silicon film.
Besides FD-SOI, it can be a bulk silicon substrate wherein a silicon film constituting the channel is isolated by a strongly doped silicon layer, e.g. dopant concentration beyond 1018 cm−3 or 1019 cm−3.
The following description will be made with reference to FD-SOI transistors as a non-limitative example.